1. Field of the Invention
The present invention relates to a data pad region of a liquid crystal display panel and a fabricating method thereof, and in particular to a data pad region of a liquid crystal display panel and a fabricating method thereof for preventing damage to a data pad region and for securing an electrical contact area.
2. Discussion of the Related Art
In general, a liquid crystal display device displays a desired image by individually supplying a data signal to liquid crystal cells arranged in a matrix form and controlling light transmittance of the liquid crystal cells according to image information. The liquid crystal display device includes a liquid crystal display panel with the liquid crystal cells arranged in a matrix form and a driving unit for driving the liquid crystal cells in each of the liquid crystal cells. The liquid crystal display panel includes a color filter substrate and a thin film transistor array substrate attached with a space therebetween, and a liquid crystal layer formed within the space between the color filter substrate and the thin film transistor array substrate.
A common electrode and a pixel electrode are formed facing each other on inner surfaces of the color filter substrate and the thin film transistor array substrate such that an electric field can be applied to the liquid crystal layer. The pixel electrode is formed in every liquid crystal cell of the thin film transistor array substrate, while the common electrode is integrally formed at the entire surface of the color filter substrate. By controlling a voltage applied to the pixel electrode while the common electrode is receiving another voltage, light transmittance of liquid crystal cells can be individually controlled. To control the voltage applied to the pixel electrode by liquid crystal cells, each liquid crystal cell includes a thin film transistor used as a switching device. On the thin film transistor array substrate of the liquid crystal display panel, a plurality of data lines for transmitting image information from a data driving unit to the liquid crystal cells and a plurality of gate lines for transmitting a scan signal from a gate driving unit to the liquid crystal cells intersect to define liquid crystal cells that are adjacent to every intersection of the data lines and gate lines. The gate driving unit sequentially supplies a scan signal to the gate lines, so that gate lines of liquid crystal cells arranged in the matrix can be selected one by one while image information is supplied to a selected line of the liquid crystal cells from the data driving unit by way of the data lines. Parts of the liquid crystal display device will be described in detail with reference to accompanying drawings.
FIG. 1 is a plan view illustrating a unit pixel of liquid crystal display device in accordance with a related art. As shown in FIG. 1, gate lines 4−1 and 4 are horizontally arranged at regular intervals, and data lines 2 and 2+1 are vertically arranged at regular intervals. Accordingly, the gate lines 4−1 and 4 and the data lines 2 and 2+1 cross each other. A unit pixel is defined within the rectangular region formed by the crossing gate lines 4−1 and 4 and data lines 2 and 2+1. The unit pixel includes a thin film transistor (TFT) and a pixel electrode 14.
The thin film transistor (TFT) includes a gate electrode 10 extending from the gate line 4; a source electrode 8 extending from the data line 2 so as to be partly overlapping with the gate electrode 10; and a drain electrode 12 that corresponds to the source electrode 8 across from the gate electrode 10. The source electrode 8 and the drain electrode 12 are formed over the gate electrode 10 so as to be separated. The drain electrode 12 is electrically connected to a pixel electrode 14 through a drain contact hole 16. The pixel electrode 14 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).
In addition, the thin film transistor (TFT) includes a semiconductor layer (not shown) that becomes a conductive channel between the source electrode 8 and the drain electrode 12 when a scan signal is supplied to the gate electrode 10. The scan signal is supplied to the gate electrode 10 from the gate line 4. When the conductive channel is formed between the source electrode 8 and the drain electrode 12 of the thin film transistor (TFT), a data signal supplied to the source electrode 8 from the data line 2 is transmitted to the drain electrode 12 via the conductive channel.
Because the drain electrode 12 is electrically connected to the pixel electrode 14 through the drain contact hole 16, the data signal supplied to the drain electrode 12 is applied to the pixel electrode 14. Thus, the pixel electrode 14 receives the data signal and generates an electric field across the liquid crystal layer with a common electrode (not shown) formed on a color filter substrate. When the electric field is applied to the liquid crystal layer, the liquid crystal is rotated by dielectric anisotropy and transmits light from a back light. The polarization of transmitted light is adjusted by a voltage value of the data signal.
The pixel electrode 14 also contacts to a storage electrode 20 through a storage contact hole 22. The storage electrode 20 is operated as a storage capacitor 18 by being overlapped with a preceding gate line 4−1 with a gate insulating layer (not shown) therebetween. Accordingly, the storage capacitor 18 charges to a voltage value of the data signal for a turn-on period of the thin film transistor (TFT) in which the scan signal is applied to the gate line 4. Afterward, the storage capacitor 18 supplies the charged voltage to the pixel electrode 14 during a turn-off period of the thin film transistor (TFT) such that operation of the liquid crystal is maintained.
FIG. 2 is an exemplary view illustrating a section of a unit pixel taken along a line I–I′ in FIG. 1. As shown in FIG. 2, the liquid crystal display panel includes a color filter substrate 60 and a thin film transistor array substrate 50 attached with a space maintained therebetween by a spacer 70. A liquid crystal layer 80 is positioned within the space between the thin film transistor array substrate 50 and the color filter substrate 60.
Fabrication processes of a thin film transistor will be described with reference to FIG. 2. First, a gate electrode 10 is formed by applying metal material on the thin film transistor array substrate 50 and pattering the metal material. Then, a gate insulating layer 30 is formed by depositing an insulating material at an upper surface of the thin film transistor array substrate 50 on which the gate electrode 10 is formed. An active layer 36 is formed on the gate insulating layer 30 by sequentially depositing a semiconductor layer 32 made of amorphous silicon and an ohmic contact layer 34 made of n+ amorphous silicon doped with phosphorus (P) at high concentration and patterning the semiconductor layer 32 and the ohmic contact layer 34. By depositing metal material on the gate insulating layer 30 and the ohmic contact layer 34 and patterning the metal material, the source electrode 8 and the drain electrode 12 of the thin film transistor (TFT) are formed. The source electrode 8 and the drain electrode 12 are patterned so as to be separated on the surface of the active layer 36.
The ohmic contact layer 34 is exposed on the surface of the active layer 36 between the source electrode 8 and the drain electrode 12. The exposed ohmic contact layer 34 is removed in the patterning process of the source electrode 8 and the drain electrode 12. Subsequently, semiconductor layer 32 is exposed between the source electrode 8 and the drain electrode 12 by removing the ohmic contact layer 34, and the exposed semiconductor layer 32 is a channel region of the thin film transistor (TFT).
A passivation film 38 is then formed by depositing an insulating material on the gate insulating layer 30 on which the source electrode 8 and the drain electrode 12 were formed including the exposed semiconductor layer 32. A drain contact hole 16 exposing a portion of the drain electrode 12 is formed by selectively etching a portion of the passivation film 38 on the drain electrode 12. By forming a transparent electrode material on the passivation film 38 and patterning the transparent electrode material, the pixel electrode 14 is formed so as to be connected to the drain electrode 12 through the drain contact hole 16.
After forming an aligning layer 51 on the surface of the resultant structure, a rubbing process is performed. More particularly, the surface of the aligning layer 51 is rubbed by a fabric at a uniform pressure and speed. High molecule chains on the surface of the aligning layer 51 are aligned in a specified direction. This determines an initial aligning direction of the liquid crystal.
Fabrication processes of the storage capacitor region will now be described with reference to accompanying FIG. 2. First, the gate line 4−1 is patterned on the thin film transistor array substrate 50, and the gate insulating layer 30 is formed thereon. The gate line 4−1 is formed while the gate electrode 10 of the thin film transistor (TFT) is formed. The gate insulating layer 30 is the same as the gate insulating layer 30 of the thin film transistor (TFT). The storage electrode 20 is patterned on the surface of the gate insulating layer 30. The storage electrode 20 is formed while forming of the source electrode 8 and the drain electrode 12 of the thin film transistor (TFT), and operated as the storage capacitor 18 by being overlapped with a portion of the gate line 4−1 with the gate insulating layer 30 therebetween.
After forming the passivation film 38 on the gate insulating layer 30 and the storage electrode 20, a storage contact hole 22 is formed exposing a portion of the storage electrode 20 by etching a portion of the passivation film 38. The passivation film 38 is the same as the passivation film 38 in the thin film transistor (TFT) region, and the storage contact hole 22 is formed while forming the drain contact hole 16 of the thin film transistor (TFT). The pixel electrode 14 is then patterned on the passivation film 38, and connected to the storage electrode 20 through the storage contact hole 22. The pixel electrode 14 is the same as the pixel electrode 14 formed on the thin film transistor (TFT) region.
Fabrication processes of the color filter substrate 60 will be described with reference to FIG. 2. First, a black matrix 62 is coated on the color filter substrate 60 with specified intervals. A red (R), green (G) and blue (B) color filter 63 is formed on the surface of the color filter substrate 50 on which the black matrix 62 is formed. A common electrode 64 is formed by forming a metal material on the surface of the color filter 63 including the black matrix 62 and patterning the metal material.
After forming an aligning layer 65 on the surface of the resultant structure, a rubbing process is performed. After the thin film transistor array substrate 50 and the color filter substrate 60 is fabricated, a sealant (not shown) is formed on the thin film transistor array substrate 50, and a spacer 70 is formed on the color filter substrate 60. The spacer 70 can be formed on the thin film transistor array substrate 50 and the sealant can be formed on the color filter substrate 60. The spacer 70 can be positioned by a scattering method, such as scattering glass beads or plastic beads having a certain diameter.
After forming the sealant and the spacer 70, the thin film transistor array substrate 50 and the color filter substrate 60 are attached to each other. The attached thin film transistor array substrate 50 and the color filter 60 are cut into unit liquid crystal display panels. To improve the yield, plural liquid crystal display panels are simultaneously formed on a large-sized glass substrate. Thus, a cutting process is required.
A liquid crystal layer 80 is formed within a space between the aligning layer 51 of the thin film transistor array substrate 50 and the aligning layer 65 of the color filter substrate 60 by injecting liquid crystal into the cut unit liquid crystal panel and sealing an injection hole. After injecting liquid crystal into plural liquid crystal panels, the attached thin film transistor array substrate 50 and color filter substrate 60 are cut into unit liquid crystal panels. However, due to the increased size of a unit liquid crystal panel, it is difficult to perform a process for injecting liquid crystal uniformly.
Productivity may be lowered due to liquid crystal injection defect. Accordingly a method of injecting liquid crystal after the attached thin film transistor array substrate 50 and color filter substrate 60 that is cut into unit liquid crystal panels has been proposed. Since the unit liquid crystal panel has only a few μm (microns) of cell gap for the hundreds of cm2 area, a vacuum injection method is most frequently used, which uses a pressure difference between an inner side and an outer side of the unit liquid crystal panel, in order to effectively inject the liquid crystal thereto.
FIG. 3 is an exemplary view illustrating a section of a unit pixel taken along a line II–II′ in FIG. 1. FIG. 3 shows the gate insulating layer 30 formed on the surface of the thin film transistor array substrate 50; the data lines 2 and 2+1 patterned on the surface of the gate insulating layer 30 so as to be separated from each other; the passivation film 38 formed on the surface of the gate insulating layer 30 including the data lines 2 and 2+1; and the pixel electrode 14 patterned on the surface of the passivation film 38 in which the data lines 2 and 2+1 are separated. Although not shown in FIG. 3, as described in the thin film transistor (TFT) fabrication processes with regard to FIG. 2, the active layer 36 including the semiconductor layer 32 and the ohmic contact layer 34 may be remained on the lower portion of the data lines 2 and 2+1. Usually, the passivation film 38 is made of an inorganic thin film, such as SiNx or SiOx, etc.
By overlapping the data lines 2 and 2+1 with a portion of the pixel electrode 14 by the passivation film 38, an aperture ratio of the liquid crystal display device can be further improved. However, because the passivation film 38 is made of a thin film inorganic material, such as SiNx or SiOx, when the data lines 2 and 2+1 are overlapped with a portion of the pixel electrode 14 by the passivation film 38, signal characteristics are deteriorated because the data lines 2 and 2+1 and the pixel electrode 14 are influenced mutually (for example, parasitic capacitance). To prevent deterioration of the signal characteristics in case that the data lines 2 and 2+1 and the pixel electrode 14 are overlapped with a portion to each other by the passivation film 38, a high aperture ratio liquid crystal display device using thick film organic material such as BCB (benzocyclobutene), etc. having low dielectric constant for a material of the passivation film 38 has been suggested. The high aperture ratio liquid crystal display device will be described with reference to accompanying drawings.
FIG. 4 is an exemplary view illustrating a plan view of the high aperture ratio liquid crystal display device, and FIG. 5 is an exemplary view illustrating a section taken along a line III–III′ in FIG. 4. First, FIG. 4 has the same plan construction with FIG. 1, except for the overlapping of a portion of the pixel electrode 14 with the data lines 2 and 2+1. FIG. 5 shows the gate insulating layer 30 formed on the surface of the thin film transistor array substrate 50; the data lines 2 and 2+1 patterned on the surface of the gate insulating layer 30 so as to be separated from each other; the passivation film 48 formed on the surface of the gate insulating layer 30 including the data lines 2 and 2+1; and the pixel electrode 14 patterned on the surface of the passivation film 38 in which the data lines 2 and 2+1 are separated so as to be partly overlapped with the data lines 2 and 2+1. Although not shown in FIG. 5, as described in the thin film transistor fabrication processes in FIG. 2, the active layer 36 including the semiconductor layer 32 and the ohmic contact layer 34 may be remained on the lower portion of the data lines 2 and 2+1. By forming the passivation film 48 as a thick film by using an organic material such as BCB, etc. having low dielectric constant, although the data lines 2 and 2+1 are overlapped with a portion of the pixel electrode 14, it is possible to prevent the occurrence of mutual influence in the overlapped regions of the pixel electrode 14.
FIG. 6 is an exemplary view illustrating a schematic plan structure of the unit liquid crystal display panel. As shown in FIG. 6, a unit liquid crystal display panel 100 is constructed by attaching the thin film transistor array substrate 50 to the color filter substrate 60, an upper longer side and a left shorter side of the thin film transistor array substrate 50 protrude with respect to the color filter substrate 60. The unit liquid crystal display panel 100 includes an image display region 113 on which the gate lines and the data lines cross each other. The unit pixels are arranged in a matrix form. A gate pad region 114 is connected to the gate lines of the image display region 113. The data pad region 115 is connected to the data lines of the image display region 113.
The thin film transistor array substrate 50 and the color filter substrate 60 are separated from each other by the spacer, and attached to each other by a seal pattern 116 formed at the periphery of the image display region 113. The gate pad region 114 is formed at the edge of the thin film transistor substrate 50 in which the shorter side protrudes in comparison with the color filter substrate 60, and the data pad region 115 is formed at the edge of the thin film transistor substrate 50 in which the longer side protrudes with respect to the color filter substrate 60. In addition, the gate pad region 114 supplies scan signals from the gate driver integrated circuit to the gate lines of the image display region 113. The data pad region 115 supplies image information from the data driver integrated circuit to the data lines of the image display region 113.
FIG. 7 is detailed view illustrating a portion of the data pad region 115 in FIG. 6. As shown in FIG. 7, the data pad region includes data lines 2 and 2+1 that are vertically arranged at regular intervals and data pads 115A and 115B that are electrically connected to the end of the data lines 2 and 2+1. The data pads 115A and 115B respectively include side contacts SC1 to SC7 separated from each other at regular intervals.
FIGS. 8A to 8C are exemplary views sequentially illustrating a section construction of the data pad region 115 taken along a line IV–IV′ in FIG. 7. As shown in FIG. 8A, the gate insulating layer 30, the active layer 36, the data line 2 and the passivation film 48 made of an organic material such as BCB, etc. are sequentially formed on the surface of the thin film transistor array substrate 50. As depicted in FIG. 2, the gate insulating layer 30, the active layer 36 and the data line 2 are formed in the fabrication of the thin film transistor (TFT). As depicted in FIGS. 4 and 5, the passivation film 48 made of an organic material such as BCB, etc. is formed to improve an aperture ratio of the liquid crystal display device.
As shown in FIG. 8B, side contact holes SC1′ to SC7′ are formed by etching the passivation film 48. As described above in reference to FIG. 2, etching of the passivation film 48 is performed simultaneously in forming of the drain contact hole 16 for connecting the drain electrode 12 and the pixel electrode 14 of the thin film transistor (TFT), by a dry etching method. In general, the data line 2 is made of a conductive material such as Cr. However, according to size increase and high resolution trends of the liquid crystal display device, a width of the data line 2 has to be reduced. However, a reduced width increases resistance even though quantity of image information transmitted through the data line 2 is increasing as display panels become larger. To improve image information transmission performance, a conductive material, such as Mo, having less resistance than Cr has been recently used for the data line 2. However, a conductive material, such as Mo, used for the data line 2 can be etched by the dry etching of the passivation film 48.
The data line 2 made of a conductive material such as Mo is electrically contacted to the pixel electrode 14 at the side of the side contact holes SC1′ to SC7′. The more the number of the side contact holes SC1′ to SC7′, the more a contact area of the data line 2 and the pixel electrode 14 can be secured, and accordingly resistance can be reduced. In addition, the active layer 36 formed in fabrication of the thin film transistor (TFT) may be etched by the dry etching of the passivation film 48. Thus, by etching the data line 2 and the active layer 36, the gate insulating layer 30 is exposed to the bottom surface of the side contact holes SC1′ to SC7′.
Then, as shown in FIG. 8C, by patterning the pixel electrode 14 on the surface of the resultant structure, the pixel electrode 14 is electrically contacted to the side of the data line 2 through the side contacts SC1 to SC7. As described above with reference to FIG. 2, patterning of the pixel electrode 14 is performed simultaneously while the patterning of the pixel electrode 14 of a unit pixel, and a transparent conductive material, such as ITO, is applied to the pixel electrode 14.
In a subsequent probe inspection, needles are contacted to the data pad region 115, and a test signal is applied. In more detail, when the liquid crystal display panel is fabricated, a probe inspection for inspecting an open defect or a short defect of the gate lines and the data lines through images displayed on the image display region is performed by applying test signals to the gate lines and the data lines through the gate pad region and the data pad region. However, in the related art, because the plural side contacts SD1 to SD7 are formed on the data pad region, contact between the needles and the side contacts SD1 to SD7 can not be performed smoothly.
More particularly, the data pad region 115 has peaks and depressions because of the plural side contacts SD1 to SD7. Accordingly, when the needles are in contact, a scratch may occur on the surface of the data pad region 115 if a misalignment occurs. This causes a defect in the liquid crystal display panel. Further, replacement of damaged needles may be required.
In addition, in the data pad region 115, an inorganic material, such as SiNx or SiOx, used for the gate insulating layer 30 has good interfacial adhering characteristics. On the contrary, an organic material such as BCB used for the passivation film 48 has poor interfacial adhering characteristics. Accordingly the pixel electrode 14 can be separated from the organic passivation film 48. More particularly, if an area contacted to the passivation film 48 is wider than an area contacted to the gate insulating layer 30 exposed to the bottom surface of the side contact holes SC1′ to SC7′, the pixel electrode 14 may be easily separated from the passivation film 48.
After the liquid crystal display panel is fabricated, when a defective TAB occurs in a module process for electrically contacting the data driver integrated circuit to the data pad region 115 by a TAB (tape-automated bonding) method, the defective TAB is detached from the data pad region 115. Because the pixel electrode 14 is adhered to the TAB, a portion or whole pixel electrode 14 is separated from the passivation film 48. Accordingly, the data pad region 115 is damaged, and becomes a defect of the liquid crystal display panel. In addition, when the defective TAB is detached from the data pad region 115, the pixel electrode 14 and the passivation film 48 may be separated from the active layer 36 since the pixel electrode 14 adhered to the defective TAB.
To improve interfacial adhering characteristics of the passivation film 48 made of an organic material, such as BCB, a triple layer structure depositing an upper SiNx film/BCB film/lower SiNx film can be used as the passivation film 48. However, even in the triple layer structure, when the defective TAB is detached from the data pad region 115, the pixel electrode 14 and the upper SiNx film may separate from the BCB film since the pixel electrode 14 is adhered to the defective TAB. In addition, the pixel electrode 14, the upper SiNx film and the BCB film may separate from the lower SiNx. Thus, there is no interfacial adhering characteristics improvement in the data pad region 115 with a triple layer structure.